Positions are open for full-time in the areas of CPU and SOC architecture development.

We are looking for all levels of talent, from the entrance to advanced levels of experience.

RTL ownership - development, assessment, and refinement of RTL design to target power, performance, area, and timing goals
Validation - support test bench development and simulation for functional and performance verification
Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance

BS or MS in Computer or Electrical Engineering with 5+ years of CPU RTL experience
A thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling, and register renaming, out-of-order execution, integer, and floating point execution, load/store execution, cache, and memory subsystems
Knowledge of Verilog and/or VHDL
Experience with simulators and waveform debugging tools
Knowledge of logic design principles along with timing and power implications
Understanding of low power microarchitecture techniques
Understanding of high performance techniques and trade-offs in a CPU microarchitecture
Experience using an interpretive language such as Perl or Python

All your information will be kept confidential according to EEO guidelines.